The present disclosure relates generally to testing a circuit design, and more specifically to testing such circuit using a programmable emulation tool having improved performance.
Integrated circuit (IC) designers commonly describe their designs in hardware description language (HDL) such as Verilog, VHDL, SystemC, and the like. In IC design, hardware emulation may refer to the process of replicating behavior of one or more pieces of hardware such as a circuit design, hereinafter also referred to as a design under test (DUT), with another piece of hardware, such as a special-purpose emulation system. An emulation model is usually generated in accordance with a HDL source code representing the design under test. The emulation model is compiled into a format used to program the emulation system that may include one or more field programmable gate array (FPGA). Thereby, the DUT is mapped by the compiler into the FPGA of the emulator system. Running the emulation system that has been programmed with the emulation model enables debugging and functional verification of the DUT. Overall progress of the emulation is usually controlled by a master clock signal generated on the emulator hardware.
A DUT, such as for example an application specific IC (ASIC), may include a complex clock structure called a clock tree, hereinafter also referred to as a “clock cone,” that may use dedicated, low-skew, signal routing resources in the ASIC chip to prevent the problem of clock skew in the physical implementation of the ASIC. In contrast, an FPGA may include a limited number of low-skew signal paths that are available for mapping portions of the clock tree into the FPGA. When low-skew signal paths are used up in an FPGA during the mapping procedure, emulation compilers have introduced additional latches to the original DUT to provide delays to avoid timing violations caused by excessive clock skew in the FPGA. However, such additional latches consume more FPGA resources, which increases the area of the FPGA that is needed to implement the emulation of the DUT, which in-turn may increase emulator complexity and/or reduce speed performance of the emulator system.
With recent technology advances, circuit designs have used more and more complex clock trees. Therefore, there is a need for reducing the use of low-skew signal resources in FPGA when efficiently mapping a complex clock tree of a DUT to a hardware emulation system without having to introduce additional delay circuits.